SUBJECT NAME: VLSI DESIGN. SUBJECT CODE: EC UNIT I CMOS TECHNOLOGY. PART –A (2 MARKS). 1. What are four generations of Integration. EC / EC64 VLSI Design 2 Marks With Answers ECE 6th Semester Regulation | BE Electronics and Communication Engineering. Sixth Semester. 2 MARK QUESTION AND ANSWERS. ECVLSI DESIGN is CMOS technology? Complementary Metal Oxide Semiconductor (CMOS)in which.
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What are the various ways to reduce the delay time of a CMOS inverter?
Give the different bitwise operators. What are the different methods of programming of PALS? Reduce activity factor Reduce supply voltage Magks is the test access port?
Remember me on this computer. Level-sensitive timing control 49 Give the different arithmetic operators? But in the moore state machine we can calculate only next state but not output from the input and state and the output is issued according to next state.
What are the different methods of programming of PALs? When a bridging fault occurs, for some combination of input conditions a measurable DC IDD will flow. What are the contents of the test architecture? It is used to convey information answerw the use of color code. What is mean by PDP? It consists of n input lines and m output lines. Log In Sign Up.
Custom blocks can be embedded Manufacturing lead time is about eight weeks. Transistors with channel length less than 3 5 microns are termed as short answera devices. Other adder structures use logic optimizations to increase the performance carry bypass, carry select, carry look ahead.
Sense amplifier is needed for reading. What is the fundamental goal in Device modeling?
What is meant by controllability? Low power Dissipation High Packing density Bi directional capability What are Programmable Interconnects?
EC VLSI DESIGN Important Part A 2 Mark Part B 16 Mark Question Bank
The difference between the earliest reaching flip flop and latest reaching flip flop for a same clock domain. Reducing the product of capacitance and its switching frequency. Low input impedance 5. What is glitch power dissipation? By adjusting the body bias i.
Channels gate array Channel less gate array Only the interconnect is 1. The threshold desig of a Vldi is usually defined as the gate voltage where an inversion layer forms the interface between the insulating layer oxide and the substrate body of the transistor. Iterative logic array testing Zero gate voltage drain current Idss 6. Latch up is a condition in which the parasitic components give rise to the establishment of low resistance conducting paths between VDD and VSS with disastrous results.
These are especially important tools for layout built from large cells. Give the different types of ASIC. No Latch-up Due to absence of bulks transistor structures are denser than bulk silicon. The potential violation of the setup wjth hold violation can happen when the data is purely asynchronous and clocked synchronously. State the advantages of CMOS process. Event-based timing control 3.
Why was PAL developed? Click here to sign up.
EC – VLSI Design 2Marks with Answer and 16Marks Question
The difference between the clock maarks at the launching flip flop vs the clock reaching the destination flip flop of a timing path. What is latch up? Enter the email address you signed up with and we’ll email you a reset link. Help Center Find new research papers in: What is called static and dynamic sequencing element? Eec2354 levels Condition in hardware circuits 0 Logic zero, false condition 1 Logic one, true condition X Unknown logic value Z High impedance, floating state It can be drawn much easier and faster than a complex layout.
What is dynamic hazard? The propagation delay is smaller compare to ripple carry adder when optimal stages are used.